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Data Sheet
On the ADE7758 , if the regular succession of the zero crossings
presented above happens, the SEQERR bit (Bit 19) in the
STATUS register is set (Figure 60). If SEQERR is set in the mask
register, the IRQ logic output goes active low (see the Interrupts
section).
If the regular zero crossing succession does not occur, that is when
a negative to positive transition on Phase A followed by a
positive to negative transition on Phase B, followed by a
ADE7758
monitor threshold. The power supply and decoupling for the
part should be designed such that the ripple at AVDD does not
exceed 5 V ± 5% as specified for normal operation.
AV DD
5V
4V
negative to positive transition on Phase C, and so on, the
SEQERR bit (Bit 19) in the STATUS register is cleared to 0.
0V
TIME
To have the ADE7758 trigger SEQERR status bit when the zero
crossing regular succession does not occur, the analog inputs for
ADE7758
INTERNAL
CALCULATIONS
INACTIVE
ACTIVE
INACTIVE
Phase C and Phase B should be swapped. In this case, the Phase
B voltage input should be wired to the VCP pin, and the Phase
C voltage input should be wired to the VBP pin.
Figure 62. On-Chip, Power-Supply Monitoring
REFERENCE CIRCUIT
The nominal reference voltage at the REF IN/OUT pin is 2.42 V.
A = 0°
B = –120°
C = +120°
This is the reference voltage used for the ADCs in the
ADE7758 . However, the current channels have three input
range selections (full scale is selectable among 0.5 V, 0.25 V, and
VOLTAGE
WAVEFORMS
0.125 V). This is achieved by dividing the reference internally
by 1, ?, and ?. The reference value is used for the ADC in the
current channels. Note that the full-scale selection is only
available for the current inputs.
ZERO
CROSSINGS
A C B A C B A C B A
SEQERR BIT OF STATUS REGISTER IS SET
Figure 60. Regular Phase Sequence Sets SEQERR Bit to 1
C
The REF IN/OUT pin can be overdriven by an external source, for
example, an external 2.5 V reference. Note that the nominal
reference value supplied to the ADC is now 2.5 V and not
2.42 V. This has the effect of increasing the nominal analog
input signal range by 2.5/2.42 × 100% = 3% or from 0.5 V to
A = 0°
C = –120°
B = +120°
0.5165 V.
The voltage of the ADE7758 reference drifts slightly with
temperature; see the Specifications section for the temperature
VOLTAGE
WAVEFORMS
coefficient specification (in ppm/°C). The value of the temperature
drift varies from part to part. Because the reference is used for
all ADCs, any ×% drift in the reference results in a 2×%
ZERO
CROSSINGS
A
B
C
A
B
C
A
B
C
A
B
deviation of the meter accuracy. The reference drift resulting
from temperature changes is usually very small and typically
SEQERR BIT OF STATUS REGISTER IS NOT SET
Figure 61. Erroneous Phase Sequence Clears SEQERR Bit to 0
POWER-SUPPLY MONITOR
The ADE7758 also contains an on-chip power-supply monitor.
The analog supply (AVDD) is monitored continuously by the
ADE7758 . If the supply is less than 4 V ± 5%, the ADE7758
goes into an inactive state, that is, no energy is accumulated
when the supply voltage is below 4 V. This is useful to ensure
correct device operation at power-up and during power-down.
The power-supply monitor has built-in hysteresis and filtering.
This gives a high degree of immunity to false triggering due to
noisy supplies. When AVDD returns above 4 V ± 5%, the
ADE7758 waits 18 μs for the voltage to achieve the
recommended voltage range, 5 V ± 5% and then becomes ready
to function. Figure 62 shows the behavior of the ADE7758
much smaller than the drift of other components on a meter.
Alternatively, the meter can be calibrated at multiple temperatures.
TEMPERATURE MEASUREMENT
The ADE7758 also includes an on-chip temperature sensor. A
temperature measurement is made every 4/CLKIN seconds.
The output from the temperature sensing circuit is connected to
an ADC for digitizing. The resultant code is processed and
placed in the temperature register (TEMP[7:0]). This register
can be read by the user and has an address of 0x11 (see the
Serial Interface section). The contents of the temperature
register are signed (twos complement) with a resolution of
3°C/LSB. The offset of this register may vary significantly from
part to part. To calibrate this register, the nominal value should
be measured, and the equation should be adjusted accordingly.
when the voltage of AVDD falls below the power-supply
Rev. E | Page 27 of 72
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